Zero-Delay Analysis
Zero-delay transitions can be important
- Can significantly impact simulation time and database size
- May contain information relevant to users
OEMs need two modes of operation
- Lossy: Zero-delay filtering
- Not Lossy: Zero-delay sequencing
- VHDL: delta-cycle
- Verilog (XL & NC) would need simulator assistance
- System-Level Simulators: can avoid such transitions altogether